Slew Propagation and Optimization in VLSI Design

Abstract

Propagation of slew in design is an important aspect while performing the static timing analysis (STA) of a design. Slew has a direct impact on delay of a timing path and could make the design pass or fail the timing closure. This research paper introduces the concept of slew and how it is propagated in two different ways in the design, and how this is a problem in itself to choose between the incident-slews at a slew merging point. In static timing analysis (STA), the waveforms that change are measured in terms of how fast or slow they change. The slew is measured in terms of the time it takes to transition from one level to the other. The rate of change is defined as the slew. The slew rate has inverse relationship with the transition time. If the slew is slow, then the transition time is more and if the slew is fast, the transition time is less. In a digital circuit design, there are points where timing arcs merge. Such points could be termed as slew merging points. In such conflicts, there are two approaches to move forward. The first approach is graph-based static timing analysis. In a graph- based approach, the worst case delays are taken into consideration by taking into the account the worst case slews (slow slews) along the timing paths, for setup analysis. While in case of hold analysis, the best case delays are taken into consideration by taking into the account the best case slews (fast slews) along the timing paths. The second approach is path-based static timing analysis. In this approach, the actual delays are taken into consideration by taking into account the actual slews along the timing paths, for setup as well as hold analysis. In path-based static timing analysis, delay is computed of the timing path so as to obtain the actual delay values. Such delay calculation takes some extra amount of time. There is a trade-off between this extra calculation time and accurate delay calculation. The synthesized gate-level net-lists are sourced in the tool along with the required files. These files include liberty timing files, which include the timing information for various cells present in the design. Library exchange files are also fed in which includes the information about various metal layers used for routing. The presence of this file makes the post-route timing possible as the values of resistances and capacitances could be extracted from interconnects. Graph-based and path-based approach are followed differently on the design. In the graph-based approach, initial timing reports are generated and then after optimizing the design for slack improvement, post-route timing reports are generated which are analysed.