Efficient Counter-Driven Linearity Calibration For SHDAC In High-Speed Applications

Abstract

Achieving both high resolution and high sample rates is a major difficulty in the field of high-speed analog-to-digital conversion for 5G communications. In order to improve speed and resolution, this work presents a novel method that combines an 8-bit Sigma-Delta (ΣΔ) ADC with a 3-bit Flash analog-to-digital converter (ADC). The proposed High-Speed and Sample Hold-Digital-Analog Converter (SHDAC) may operate at sampling frequencies ranging from 1 giga-samples per second (Gsps) to 14 Gsps and across a variety of voltage sampling ranges from 2 to 32 scales. The SHDAC successfully strikes a balance between speed and accuracy by utilizing the high-speed conversion capability of the 3-bit Flash ADC and the oversampling and noise reduction advantages of the 8-bit Sigma-Delta ADC. This makes it ideal for 5G digital communication and signal processing applications. The use of a digital scaling mechanism that dynamically modifies the SHDAC's bit resolution to 4, 8, 16, or 32 bits depending on system requirements is a significant breakthrough in this architecture. Because of its versatility, the SHDAC can be used for a variety of 5G applications, such as high-precision signal processing with lower sample rates and ultra-fast data gathering with lesser resolution. High precision, scalability, and adaptability are ensured by the front-end Verilog model used to implement the suggested SHDAC architecture. The efficiency of the SHDAC is validated by Vivado simulations, which show sampling rates ranging from 1 to 14 Gsps and an ultra-low dynamic power usage of 0.0007w, Sampling rate is 4.286GSpS and SNDR value is 68.98dB, These findings demonstrate how the SHDAC with parasitic capacitance using Counter design with linear correction process for high-speed design can facilitate fast, and to energy-efficient data conversion for upcoming 5G communication systems.