Resource Optimized FIR Filter Architecture with Coefficient Reuse for ASIC Design

Abstract

This work presents the design, functional verification, and ASIC synthesis of a digital FIR filter architecture optimized through coefficient reuse. The proposed method exploits symmetry in filter coefficients to minimize redundant multiplications, thereby reducing hardware complexity without compromising accuracy. RTL implementation in Verilog was verified using simulation waveforms, confirming correct convolution behavior under varied input sequences. The design was synthesized using Cadence Genus with a 1.0 V standard cell library, achieving an area utilization of 1675 units across 482 cells. Power analysis reported a leakage of 96 nW and dynamic consumption of 26 µW, demonstrating efficiency suitable for low power signal processing applications. Timing analysis highlighted feasible propagation delays through arithmetic stages, validating the design’s readiness for ASIC integration. The results establish coefficient reuse as a practical optimization strategy, delivering a compact, power efficient, and functionally robust FIR filter architecture for advanced signal processing systems.