Advancing At-Speed Testing through Launch-on-Extra-Shift Architecture

Abstract

At-speed testing of integrated circuits presents a fundamental challenge in balancing comprehensive fault detection with power management and manufacturing yield optimization. Traditional testing methodologies force designers to compromise between test quality and power constraints, as patterns optimized for fault coverage often generate excessive switching activity that causes voltage drops and false test failures. This article explores the implementation of launch-on-extra-shift testing architecture combined with strategic power management techniques to address these competing requirements. The article examines two primary launch mechanisms for generating test transitions: launch-off-capture, which provides relaxed timing requirements but requires computationally intensive sequential pattern generation, and launch-on-extra-shift, which enables faster combinational pattern generation but introduces stringent timing constraints on scan enable signals. A sophisticated mixed-testing architecture is presented that employs pipelined scan enable structures and dynamic control capabilities through test point integration, allowing different design regions to operate under different launch mechanisms based on their specific characteristics. To mitigate the elevated switching activity inherent in launch-on-extra-shift testing, strategic clock gating techniques are implemented through a hierarchical power management infrastructure that selectively activates or deactivates circuit portions during test operations. The implementation strategy incorporates simulation-based analysis to identify power hotspots and validate design modifications through iterative refinement processes. By combining these architectural innovations with partition-based testing approaches, the methodology achieves enhanced transition fault coverage while maintaining acceptable power profiles and manufacturing economics, demonstrating that temporal and spatial separation of testing activity can preserve pattern quality while reducing instantaneous power consumption without sacrificing fault detection capabilities.